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MK2732-05 Low Phase Noise VCXO+Multiplier
Description
The MK2732-05 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The on-chip Voltage Controlled Crystal Oscillator (VCXO) accepts a 0 to 3 V input voltage to cause the output clocks to vary by 100 ppm. Using ICS/MicroClock's patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 10 MHz to 14.318 MHz pullable crystal input to produce one or two output clocks. ICS manufactures the largest variety of Set-Top Box and multimedia clock synthesizers for all applications. Consult ICS to eliminate VCXOs, crystals and oscillators from your board.
Features
* Packaged in 16 pin narrow SOIC * Replaces a VCXO and multiplier * Uses an inexpensive pullable crystal * Output clocks up to 85 MHz * On-chip patented VCXO with pull range of 200 ppm (100 ppm) minimum * VCXO tuning voltage of 0 to 3 V * Zero ppm synthesis error in both clocks * 25 mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * 5 V operating voltage for core, ability to run output clocks at 3.3V or 5V
Block Diagram
VDD5 3 Output Buffer CLK1 VDDIO
S2:S0 VIN 10-14 MHz X1 pullable crystal
X2
Voltage Controlled Crystal Oscillator
PLL/Clock Synthesis Circuitry
Output Buffer
CLK2
OE
1 Revision 122799 Printed 11/16/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126*(408) 295-9800 tel* www.icst.com
MDS 2732-05 D
MK2732-05 Low Phase Noise VCXO+Multiplier
Pin Assignment Clock Select Table
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S1 GND CLK2 VDDIO S0 CLK1
S2 0 0 0 0 0 0 1 1 1 1 1 1 S1 0 0 0 1 1 1 0 0 0 1 1 1 S0 0 M 1 0 M 1 0 M 1 0 M 1 CLK1 REF/4 OFF OFF OFF OFF OFF Test OFF OFF OFF OFF OFF CLK2 REF/2 x0.666 x2.6666 x4 x1.5 x1.3333 Test x4 x2 x3 x5 x6
MK2732-05
X1 VDD5 VDD5 VIN GND GND S2 OE
16 pin narrow (150 mil) SOIC Pin Descriptions
Number 1 2, 3 4 5, 6, 13 7 8 9 10 11 12 14 15 16 Name X1 VDD5 VIN GND S2 OE CLK1 S0 VDDIO CLK2 S1 NC X2 Type XI P VI P I I O TI P O I XO
0=connect directly to GND, 1=connect directly to VDDIO, OFF=output stopped low.
Description Crystal connection. Connect to a pullable crystal of 10-14.318 MHz. Core VDD. Connect to +5V. Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO. Connect to ground. Select input #2. Selects outputs per table above. Do not exceed VDDIO. Output Enable. Tri-states outputs when low. Do not exceed VDDIO. Clock Output #1 per table above. Amplitude = VDDIO. Select input #0. Selects outputs per table above. Do not exceed VDDIO. Input and output VDD. Connect to +3.3V or +5V. Clock amplitude matches this voltage. Clock Output #2 per table above. Amplitude = VDDIO. Select input #1. Selects outputs per table above. Do not exceed VDDIO. Nothing is connected internally to this pin. Crystal connection. Connect to a pullable crystal of 10-14.318 MHz.
Key: I = Input with internal pull-up resistor; TI = tri-level input; O = output; P = power supply connection; VI = analog voltage input; XI, XO = crystal pins.
External Components
The MK2732-05 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD5 and GND on pins 3 and 5, and VDDIO and GND on pins 11 and 13, as close to the MK2732-05 as possible. A series termination resistor of 33 may be used for each clock output. The input crystal must be connected as close to the chip as possible. The input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load capacitance is recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT consult the application note MAN05 for layout guidelines. 2 Revision 122799 Printed 11/16/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126*(408) 295-9800 tel* www.icst.com
MDS 2732-05 D
MK2732-05 Low Phase Noise VCXO+Multiplier
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Core Operating Voltage, VDD5 I/O Operating Voltage, VDDIO Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH, binary inputs Input Low Voltage, VIL, binary inputs Input High Voltage, VIH, trinary input Input Low Voltage, VIL, trinary input Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Short Circuit Current Input Capacitance Frequency synthesis error VIN, VCXO control voltage Input Crystal Frequency Output Clock Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter Phase Noise, relative to carrier Output pullability, note 2 Notes: Conditions Referenced to GND Referenced to GND Max of 10 seconds -65 4.75 3.15 3.5 S2, S1, OE S2, S1, OE S0, pin 10 S0, pin 10 IOH=-25mA IOL=25mA IOH=-8mA No Load Each output S2:S0, OE Both clocks 2 0.8 VDDIO-0.5 0.5 2.4 0.4 VDDIO-0.4 19 100 7 0 10 2.5 0.8 to 2.0V 2.0 to 0.8V At VDDIO/2 10 kHz offset 0V VIN 3V 0 3 14.31818 85.9 1.5 1.5 60 100 -115 100 5.0 3.3 2.5 2.5 Minimum Typical Maximum 7 VDD+0.5 70 260 150 5.25 VDD5 1.5 Units V V C C C V V V V V V V V V V V mA mA pF ppm V MHz MHz ns ns % ps dBc/Hz ppm
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0
DC CHARACTERISTICS (VDD5 = 5.0V unless noted)
AC CHARACTERISTICS (VDD5 = 5.0V unless noted)
40
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With an ICS/MicroClock approved pullable crystal. 14 pF 240 max 35 max 0 to 70 C 20 ppm 50 ppm
Pullable Crystal Specifications:
Correlation (load) Capacitance CO/C1 ESR Operating Temperature Initial Accuracey Temperature plus Aging Stability
MDS 2732-05 D
3 Revision 122799 Printed 11/16/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126*(408) 295-9800 tel* www.icst.com
MK2732-05 Low Phase Noise VCXO+Multiplier
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Symbol A
A1
E
H
B
C
D A1 e
Ordering Information
Part/Order Number MK2732-05S MK2732-05STR
h x 45 A L
D E e H h L
Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.075 0.098 0.3859 0.3937 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500
Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 1.91 2.40 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27
C B
Marking MK2732-05S MK2732-05S
Shipping packaging tubes tape and reel
Package 16 pin SOIC 16 pin SOIC
Temperature 0-70 C 0-70 C
Revision history: Version Revision A 10308 B 12078 C D 4289 12279 Comments Original CLK1 and CLK2 functions switched in 000 address, changed from x0.75 to x0.666 in 00M address, changed name of VDD3.3 to VDDIO. Added jitter spec, changed VDD on VIH and VOH to VDDIO, lowered IDD. Added L dimension, changed address. Eliminated "Preliminary". Changed to JEDEC dimensions. Changed VDD to 5%. Added Pullable Crystal Specifications.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
4 Revision 122799 Printed 11/16/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126*(408) 295-9800 tel* www.icst.com
MDS 2732-05 D

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